3822 datasheet(15/59 Pages) RENESAS

15 / 59 page

Rev.1.20

Dec 24, 2003

page 15 of 57

3822 Group (A ver.)

Real time port

function output

A-D conversion input

A-D trigger input

Diagram No.

Related SFRs

Input/Output

Name

Non-Port Function

I/O Format

Table 6 List of I/O port function

P00/SEG16–

P07/SEG23

P10/SEG24–

P17/SEG31

P20–P27

P34/SEG12–

P37/SEG15

P40

P41/

P42/INT0,

P43/INT1

P44/RXD

P45/TXD

P46/SCLK

P47/SRDY

P50/INT2,

P51/INT3

P52/RTP0,

P53/RTP1

P54/CNTR0

Port P0

Port P1

Port P2

Port P3

Port P4

Input/output,

individual ports

Input/output,

individual bits

Input

Input/output,

individual bits

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS compatible

input level

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

LCD segment output

Key input (key-on

wake-up) interrupt

input

LCD segment output

φ clock output

External interrupt input

Serial I/O function I/O

External interrupt input

Timer X function I/O

Timer Y function input

Timer 2 function output

PULL register A

Segment output enable

PULL register A

Interrupt control register 2

PULL register A

Segment output enable

PULL register B

φ output control register

PULL register B

Interrupt edge selection

PULL register B

Serial I/O control register

Serial I/O status register

UART control register

PULL register B

Interrupt edge selection

PULL register B

Timer X mode register

PULL register B

Timer X mode register

PULL register B

Timer Y mode register

PULL register B

Timer 123 mode register

PULL register B

A-D control register

PULL register A

CPU mode register

(1)

(2)

(3)

(4)

(6)

(5)

(2)

(8)

(7)

Port P5

(9)

(2)

Input/output,

individual bits

(10)

P55/CNTR1

(11)

(12)

(13)

(12)

(14)

P56/TOUT

P57/ADT

P60/AN0–

P67/AN7

(15)

P70/XCOUT

P71/XCIN

COM0–COM3

SEG0–SEG11

(16)

(17)

(18)

Input/output,

individual bits

Input/output,

individual bits

Output

Sub-clock

generating circuit I/O

LCD common output

LCD segment output

Port P6

Port P7

Common

Segment

LCD mode register

Notes 1: For details of how to use double function ports as function I/O ports, refer to the applicable sections.

2: When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

Especially, power source current may increase during execution of the STP and WIT instructions.

Fix the unused input pins to “H” or “L” through a resistor.

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