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3822 Datasheet(PDF) 18 Page - Renesas Technology Corp |
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3822 Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 59 page ![]() Rev.1.20 Dec 24, 2003 page 18 of 57 3822 Group (A ver.) Fig. 14 Port block diagram (3) VL2/VL3 VL1/VSS (13) Port P56 Data bus Direction register Port latch Pul-up control TOUT output control bit Timer output (14) Port P6 Data bus Direction register Port latch Pull-up control A-D conversion input Analog input pin selection bit (15) Port P70 Data bus Direction register Port latch Port XC switch bit + Pull-up control Port XC switch bit Oscillation circuit Port P71 Port XC switch bit (16) Port P71 Data bus Direction register Port latch Port XC switch bit Port XC switch bit + Pull-up control Sub-clock generating circuit input VL3 VL2 VL1 (17) COM0–COM3 (18) SEG0–SEG11 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value. |
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