3886 datasheet(49/111 Pages) RENESAS

49 / 111 page

3886 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

START/STOP

condition

control register

Oscillation

frequency

f(XIN) (MHz)

Fig. 46 Address data communication format

Fig. 45 Structure of I2C START/STOP condition control register

Note: Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).

Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency

Main clock

divide ratio

System

clock

(MHz)

SCL release time

(

µs)

Setup time

(

µs)

Hold time

(

µs)

XXX11110

XXX11010

XXX11000

XXX00100

XXX01100

XXX01010

XXX00100

3.2

µs (16 cycles)

3.5

µs (14 cycles)

3.25

µs (13 cycles)

3.0

µs (3 cycles)

3.5

µs (7 cycles)

3.0

µs (6 cycles)

3.0

µs (3 cycles)

6.2

µs (31 cycles)

6.75

µs (27 cycles)

6.25

µs (25 cycles)

5.0

µs (5 cycles)

6.5

µs (13 cycles)

5.5

µs (11 cycles)

5.0

µs (5 cycles)

3.0

µs (15 cycles)

3.25

µs (13 cycles)

3.0

µs (12 cycles)

2.0

µs (2 cycles)

3.0

µs (6 cycles)

2.5

µs (5 cycles)

2.0

µs (2 cycles)

STSP

SEL

I2C START/STOP condition

control register

START/STOP condition set bit

SCL/SDA interrupt pin polarity

selection bit

0 :Falling edge active

1 :Rising edge active

SCL/SDA interrupt pin selection bit

0 :SDA valid

1 :SCL valid

START/STOP condition generating

selection bit

0 :Setup/Hold time short mode

1 :Setup/Hold time long mode

SISSIP SSC4SSC3SSC2SSC1SSC0

(S2D : address 001716)

SSlave addressR/W

ADataA

Data

A/A

7 bits“0”1 to 8 bits1 to 8 bits

(1) A master-transmitter transnmits data to a slave-receiver

Slave address R/W

ADataA

Data

7 bits“1”1 to 8 bits1 to 8 bits

(2) A master-receiver receives data from a slave-transmitter

Slave address

1st 7 bits

R/W

7 bits“0”8 bits

(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address

Slave address

2nd bytes

DataA

Data

A/A

1 to 8 bits1 to 8 bits

Slave address

1st 7 bits

R/W

7 bits“0”8 bits

(4) A master-receiver receives data from a slave-transmitter with a 10-bit address

Slave address

2nd bytes

AData

Slave address

1st 7 bits

R/W

DataP

S : START condition

A : ACK bit

Sr : Restart condition

P : STOP condition

R/W : Read/Write bit

7 bits

“1”1 to 8 bits1 to 8 bits

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