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4524 Datasheet(PDF) 46 Page - Renesas Technology Corp

Part # 4524
Description  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  161 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4524 Datasheet(HTML) 46 Page - Renesas Technology Corp

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Rev.2.00
Jul 27, 2004
page 46 of 159
REJ03B0091-0200Z
4524 Group
VSS
VDD
IAP2
(P20–P23)
IAP3
(P30–P33)
OP2A
(P20–P23)
OP3A
(P30–P33)
TABAD
1/6
Q13
Q21 Q20
Q22
TADAB
Q12 Q11 Q10
0
1
4
4
4
4
8
8
8
01
1
8
10
Q13
Q13
0
1
Q13
8
8
2
TALA
Q13
Q23
TAQ2
TQ2A
TAQ1
TQ1A
ADF
(1)
P20/AIN0
P30/AIN4
P31/AIN5
P32/AIN6
P33/AIN7
3
1
0
10
P21/AIN1
P22/AIN2
P23/AIN3
4
4
Q31 Q30
Q32
Q33
TAQ3
TQ3A
4
DA converter
(Note 1)
Register A (4)
Register B (4)
DAC
operation
signal
Comparator
Instruction clock
A/D control circuit
Successive comparison
register (AD) (10)
A/D
interrupt
Comparator register (8)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1).
The value of the comparator register is retained even when the mode is switched to the A/D conversion
mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.
(Note 2)
A/D CONVERTER (Comparator)
The 4524 Group has a built-in A/D conversion circuit that performs
conversion by 10-bit successive comparison method. Table 11
shows the characteristics of this A/D converter. This A/D converter
can also be used as an 8-bit comparator to compare analog volt-
ages input from the analog input pin with preset values.
Table 11 A/D converter characteristics
Characteristics
Successive comparison method
10 bits
Linearity error: ±2LSB
Differential non-linearity error: ±0.9LSB
31
µs (High-speed through-mode at 6.0
MHz oscillation frequency)
8
Parameter
Conversion format
Resolution
Relative accuracy
Conversion speed
Analog input pin
Fig. 33 A/D conversion circuit structure



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