4524 datasheet(33/161 Pages) RENESAS

33 / 161 page

Rev.2.00

Jul 27, 2004

page 33 of 159

REJ03B0091-0200Z

4524 Group

Fig. 25 Timer structure (1)

STCK

W22

W21, W20

ORCLK

T1UDF

PWMOUT

T2F

(TAB2)

(T2AB)

T1UDF

W23

1/2

T2UDF

1/2

W60

Port D7 output

D7/CNTR0

Division circuit

Divided by 8

Divided by4

Divided by 2

System clock (STCK)

XCIN

Instruction clock

(INSTCK)

Multi-

plexer

(CMCK/CRCK)

Quartz-crystal

oscillation

MR0

ORCLK

Reload register RPS (8)

Prescaler (8)

(TABPS)

(TPSAB)

PA0

MR3, MR2

INSTCK

I12

D8/INT0

W13

T1UDF

I10

I13

I11

I10

W12

W11, W10

ORCLK

T5UDF

D7/CNTR0

T1F

(TAB1)

(T1AB)

(TR1AB)

(TPSAB)

PWMOUT

I22

D9/INT1

W33

T3UDF

I20

I23

I21

I20

W32

W31, W30

ORCLK

T2UDF

C/CNTR1

T3F

(TAB3)

(T3AB)

(TR3AB)

T5UDF:

PWMOUT:

Timer 5 underflow signal (from timer 5)

PWM output signal (from timer 4 output unit)

(Note 1)

(Note 2)

(Note 4)

(Note 3)

(Note 4)

On-chip oscillator

XIN

Ceramic resonance

(CMCK)

RC oscillation

(CRCK)

Timer 1 (8)

Timer 1

interrupt

Reload register R1 (8)

Timer 1 underflow signal (T1UDF)

One-sided edge

detection circuit

Both edges

detection circuit

Falling

Rising

(Note 4)

One-sided edge

detection circuit

Both edges

detection circuit

Falling

Rising

Timer 2

interrupt

Timer 2 underflow signal (T2UDF)

Timer 2 (8)

Reload register R2 (8)

Timer 3

interrupt

Timer 3 underflow signal (T3UDF)

Timer 3 (8)

Reload register R3 (8)

Internal clock

generating circuit

(divided by 3)

Data is set automatically from each reload

(auto-reload function).

Notes 1: When CMCK instruction is executed, ceramic resonance is selected.

When CRCK instruction is executed, RC oscillation is selected.

When any instructions are not executed, on-chip oscillator clock

(internal oscillation) is selected.

2: Timer 1 count start synchronous circuit is set

by the valid edge of D8/INT0 pin selected by bits 1 (I11) and 2 (I12)

of register I1.

3: Timer 3 count start synchronous circuit is set

by the valid edge of D9/INT1 pin selected by bits 1 (I21) and 2 (I22)

of register I2.

4: Count source is stopped by clearing to “0.”

4524 Datasheet(PDF) 33 Page - Renesas Technology Corp

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