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4524 Datasheet(PDF) 63 Page - Renesas Technology Corp |
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4524 Datasheet(HTML) 63 Page - Renesas Technology Corp |
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63 / 161 page ![]() Rev.2.00 Jul 27, 2004 page 63 of 159 REJ03B0091-0200Z 4524 Group Fig. 49 Structure of reset pin and its peripherals,, and power-on reset operation Name D0–D3 D4/SIN, D5/SOUT, D6/SCK D7/CNTR0 D8/INT0, D9/INT1 P00–P03 P10–P13 P20/AIN0–P23/AIN3 P30/AIN4–P33/AIN7 P40–P43 C/CNTR1 Notes 1: Output latch is set to “1.” 2: Output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF. Function D0–D3 D4–D6 D7 D8, D9 P00–P03 P10–P13 P20–P23 P30–P33 P40–P43 C State High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Note 1) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Note 1) High-impedance (Note 1) High-impedance (Notes 1, 2) “L” (VSS) level (1) Power-on reset Reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V must be set to 100 µs or less. If the rising time ex- ceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating volt- age. Table 19 Port state at reset RESET pin WEF Watchdog reset signal (Note 1) Pull-up transistor (Note 1) Power-on reset circuit Voltage drop detection circuit VDD (Note 3) 100 µs or less (Note 2) Internal reset signal Power-on Reset released Internal reset signal Reset state Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Power-on reset circuit output |
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