SH7206 datasheet(13/1188 Pages) RENESAS

13 / 1188 page

Rev. 3.00 Jun. 18, 2008 Page xiii of xxiv

7.4.1

Address Array ....................................................................................................... 194

7.4.2

Data Array ............................................................................................................ 195

7.4.3

Usage Examples.................................................................................................... 197

7.4.4

Notes ..................................................................................................................... 198

Section 8 Bus State Controller (BSC)................................................................199

8.1

Features.............................................................................................................................. 199

8.2

Input/Output Pins ...............................................................................................................202

8.3

Area Overview ...................................................................................................................204

8.3.1

Address Map ......................................................................................................... 204

8.3.2

Data Bus Width and Pin Function Setting in Each Area....................................... 205

8.4

Register Descriptions ......................................................................................................... 206

8.4.1

Common Control Register (CMNCR) .................................................................. 208

8.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0 to 8) ..................................... 211

8.4.3

CSn Space Wait Control Register (CSnWCR) (n = 0 to 8) .................................. 216

8.4.4

SDRAM Control Register (SDCR)....................................................................... 253

8.4.5

Refresh Timer Control/Status Register (RTCSR)................................................. 257

8.4.6

Refresh Timer Counter (RTCNT)......................................................................... 259

8.4.7

Refresh Time Constant Register (RTCOR) .......................................................... 260

8.4.8

AC Characteristics Switching Register (ACSWR) ............................................... 261

8.4.9

AC Characteristics Switching Key Register (ACKEYR) ..................................... 262

8.4.10 Sequence to Write to ACSWR.............................................................................. 263

8.5

Operation ........................................................................................................................... 264

8.5.1

Endian/Access Size and Data Alignment.............................................................. 264

8.5.2

Normal Space Interface......................................................................................... 267

8.5.3

Access Wait Control ............................................................................................. 272

8.5.4

CSn Assert Period Expansion ............................................................................... 274

8.5.5

MPX-I/O Interface ................................................................................................ 275

8.5.6

SDRAM Interface ................................................................................................. 279

8.5.7

Burst ROM (Clocked Asynchronous) Interface.................................................... 323

8.5.8

SRAM Interface with Byte Selection.................................................................... 325

8.5.9

PCMCIA Interface ................................................................................................ 330

8.5.10 Burst MPX-I/O Interface ...................................................................................... 337

8.5.11 Burst ROM (Clocked Synchronous) Interface ...................................................... 342

8.5.12 Wait between Access Cycles ................................................................................ 343

8.5.13 Bus Arbitration ..................................................................................................... 350

8.5.14 Others.................................................................................................................... 352

8.6

Usage Notes ....................................................................................................................... 355

8.6.1

Burst ROM Interface ............................................................................................ 355

8.6.2

PCMCIA I/O Card Interface ................................................................................. 355

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