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SH7206 Datasheet(PDF) 30 Page - Renesas Technology Corp |
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SH7206 Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 1188 page ![]() Section 1 Overview Rev. 3.00 Jun. 18, 2008 Page 6 of 1160 REJ09B0191-0300 Items Specification I 2C bus interface 3 (IIC3) • One channel • Master mode and slave mode supported I/O ports • Input or output can be selected for each bit • Internal weak keeper circuit A/D converter (ADC) • 10-bit resolution • Eight input channels • Conversion can be carried out simultaneously on two channels. • A/D conversion request by the external trigger or timer trigger D/A converter (DAC) • 8-bit resolution • Two output channels User break controller (UBC) • Two break channels • Addresses, data values, type of access, and data size can all be set as break conditions High-performance user debugging interface (H-UDI) • E10A emulator support • JTAG-standard pin assignment On-chip RAM • Four pages • 128-Kbyte large-capacity memory Power supply voltage • Vcc: 1.15 to 1.35 V • PVcc: 3.0 to 3.6 V Packages • LQFP2424-176Cu (0.5 pitch) |
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