SH7261 datasheet(410/1348 Pages) RENESAS

410 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 378 of 1312

REJ09B0320-0200

Figure 12.1 shows a block diagram of the MTU2.

Input/output pins

Channel 3: TIOC3A

TIOC3B

TIOC3C

TIOC3D

Channel 4: TIOC4A

TIOC4B

TIOC4C

TIOC4D

Input pins

Channel 5: TIC5U

TIC5V

TIC5W

Interrupt request signals

Channel 3: TGIA_3

TGIB_3

TGIC_3

TGID_3

TCIV_3

Channel 4: TGIA_4

TGIB_4

TGIC_4

TGID_4

TCIV_4

Channel 5: TGIU_5

TGIV_5

TGIW_5

Clock input

Internal clock:

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

External clock: TCLKA

TCLKB

TCLKC

TCLKD

Interrupt request signals

Channel 0: TGIA_0

TGIB_0

TGIC_0

TGID_0

TGIE_0

TGIF_0

TCIV_0

Channel 1: TGIA_1

TGIB_1

TCIV_1

TCIU_1

Channel 2: TGIA_2

TGIB_2

TCIV_2

TCIU_2

Input/output pins

Channel 0: TIOC0A

TIOC0B

TIOC0C

TIOC0D

Channel 1: TIOC1A

TIOC1B

Channel 2: TIOC2A

TIOC2B

Peripheral bus

A/D converter conversion

start signal

[Legend]

TSTR: Timer start register

TSYR: Timer synchronous register

TCR:

Timer control register

TMDR: Timer mode register

TIOR:

Timer I/O control register

TIORH: Timer I/O control register H

TIORL: Timer I/O control register L

TIER:

Timer interrupt enable register

TGCR: Timer gate control register

TOER: Timer output master enable register

TOCR: Timer output control register

TSR:

Timer status register

TCNT: Timer counter

TCNTS: Timer subcounter

TCDR:

Timer cycle data register

TCBR:

Timer cycle buffer register

TDDR:

Timer dead time data register

TGRA:

Timer general register A

TGRB:

Timer general register B

TGRC:

Timer general register C

TGRD:

Timer general register D

TGRE:

Timer general register E

TGRF:

Timer general register F

TGRU:

Timer general register U

TGRV:

Timer general register V

TGRW: Timer general register W

Figure 12.1 Block Diagram of MTU2

SH7261 Datasheet(PDF) 410 Page - Renesas Technology Corp

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