SH7261 datasheet(418/1348 Pages) RENESAS

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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 386 of 1312

REJ09B0320-0200

12.3.1

Timer Control Register (TCR)

The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each

channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three

(TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted

only when TCNT operation is stopped.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

CCLR[2:0]

CKEG[1:0]

TPSC[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

7 to 5

CCLR[2:0]

000

R/W

Counter Clear 0 to 2

These bits select the TCNT counter clearing source.

See tables 12.4 and 12.5 for details.

4, 3

CKEG[1:0]

R/W

Clock Edge 0 and 1

These bits select the input clock edge. When the input

clock is counted using both edges, the input clock

period is halved (e.g. P

φ/4 both edges = Pφ/2 rising

edge). If phase counting mode is used on channels 1

and 2, this setting is ignored and the phase counting

mode setting has priority. Internal clock edge selection

is valid when the input clock is P

φ/4 or slower. When

φ/1, or the overflow/underflow of another channel is

selected for the input clock, although values can be

written, counter operation compiles with the initial value.

00: Count at rising edge

01: Count at falling edge

1x: Count at both edges

2 to 0

TPSC[2:0]

000

R/W

Time Prescaler 0 to 2

These bits select the TCNT counter clock. The clock

source can be selected independently for each channel.

See tables 12.6 to 12.10 for details.

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