SH7261 datasheet(422/1348 Pages) RENESAS

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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 390 of 1312

REJ09B0320-0200

Table 12.10 TPSC1 and TPSC0 (Channel 5)

Channel

Bit 1

TPSC1

Bit 0

TPSC0

Description

Internal clock: counts on P

φ/1

Internal clock: counts on P

φ/4

Internal clock: counts on P

φ/16

Internal clock: counts on P

φ/64

Note:

Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value

should always be 0.

12.3.2

Timer Mode Register (TMDR)

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of

each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register

settings should be changed only when TCNT operation is stopped.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

—

BFE

BFB

BFA

MD[3:0]

Bit

Bit Name

Initial

Value

R/W

Description

—

Reserved

This bit is always read as 0. The write value should

always be 0.

BFE

R/W

Buffer Operation E

Specifies whether TGRE_0 and TGRF_0 are to operate

in the normal way or to be used together for buffer

operation.

When TGRF is used as a buffer register, TGRF

compare match is generated.

In channels 1 to 4, this bit is reserved. It is always read

as 0 and the write value should always be 0.

0: TGRE_0 and TGRF_0 operate normally

1: TGRE_0 and TGRF_0 used together for buffer

operation

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