SH7261 datasheet(423/1348 Pages) RENESAS

423 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 391 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

BFB

R/W

Buffer Operation B

Specifies whether TGRB is to operate in the normal

way, or TGRB and TGRD are to be used together for

buffer operation. When TGRD is used as a buffer

generated in other than complementary PWM mode.

TGRD compare match is generated in complementary

PWM mode. When compare match occurs during the tb

period in complementary PWM mode, TGRD is set.

Therefore, set the TGIED bit in the timer interrupt

enable register_3/4 (TIER_3/4) to 0.

In channels 1 and 2, which have no TGRD, bit 5 is

reserved. It is always read as 0 and cannot be modified.

0: TGRB and TGRD operate normally

1: TGRB and TGRD used together for buffer operation

BFA

R/W

Buffer Operation A

Specifies whether TGRA is to operate in the normal

way, or TGRA and TGRC are to be used together for

buffer operation. When TGRC is used as a buffer

generated in other than complementary PWM mode.

TGRC compare match is generated in complementary

PWM mode. When compare match for channel 4

occurs during the tb period in complementary PWM

mode, TGFC is set. Therefore, set the TGIEC bit in the

timer interrupt enable register_4 (TIER_4) to 0.

In channels 1 and 2, which have no TGRC, bit 4 is

reserved. It is always read as 0 and cannot be modified.

0: TGRA and TGRC operate normally

1: TGRA and TGRC used together for buffer operation

3 to 0

MD[3:0]

0000

R/W

Modes 0 to 3

These bits are used to set the timer operating mode.

See table 12.11 for details.

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