SH7261 datasheet(444/1348 Pages) RENESAS

444 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 412 of 1312

REJ09B0320-0200

12.3.4

Timer Compare Match Clear Register (TCNTCMPCLR)

TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5,

TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

—————

CMP

CLR5U

CMP

CLR5V

CMP

CLR5W

Bit

Bit Name

Initial

Value

R/W

Description

7 to 3

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CMPCLR5U 0

R/W

TCNT Compare Clear 5U

Enables or disables requests to clear TCNTU_5 at

TGRU_5 compare match or input capture.

0: Disables TCNTU_5 to be cleared to H'0000 at

TCNTU_5 and TGRU_5 compare match or input

capture

1: Enables TCNTU_5 to be cleared to H'0000 at

TCNTU_5 and TGRU_5 compare match or input

capture

CMPCLR5V 0

R/W

TCNT Compare Clear 5V

Enables or disables requests to clear TCNTV_5 at

TGRV_5 compare match or input capture.

0: Disables TCNTV_5 to be cleared to H'0000 at

TCNTV_5 and TGRV_5 compare match or input

capture

1: Enables TCNTV_5 to be cleared to H'0000 at

TCNTV_5 and TGRV_5 compare match or input

capture

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