SH7261 datasheet(445/1348 Pages) RENESAS

445 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 413 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

CMPCLR5W 0

R/W

TCNT Compare Clear 5W

Enables or disables requests to clear TCNTW_5 at

TGRW_5 compare match or input capture.

0: Disables TCNTW_5 to be cleared to H'0000 at

TCNTW_5 and TGRW_5 compare match or input

capture

1: Enables TCNTW_5 to be cleared to H'0000 at

TCNTW_5 and TGRW_5 compare match or input

capture

12.3.5

Timer Interrupt Enable Register (TIER)

The TIER registers are 8-bit readable/writable registers that control enabling or disabling of

interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and

one each for channels 1 to 5.

• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4

76543210

Bit:

Initial value:

R/W:

00000000

R/W

TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA

Bit

Bit Name

Initial

Value

R/W

Description

TTGE

R/W

A/D Converter Start Request Enable

Enables or disables generation of A/D converter start

requests by TGRA input capture/compare match.

0: A/D converter start request generation disabled

1: A/D converter start request generation enabled

SH7261 Datasheet(PDF) 445 Page - Renesas Technology Corp

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