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SH7261 Datasheet(PDF) 962 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 962 Page - Renesas Technology Corp |
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962 / 1348 page  Section 20 IEBus TM Controller (IEB) [R5S72612] [R5S72613] Rev. 2.00 Sep. 07, 2007 Page 930 of 1312 REJ09B0320-0200 20.5 Software Control Flows 20.5.1 Initial Setting Figure 20.8 shows the flowchart for the initial setting. Start End [IECTR register setting] Pin porarity setting Receive enable Notes: 1. As for setting of PDCR4 register in PFC, see section 25, Pin Function Controller (PFC). 2. As for setting of STBCR2 register, see section 27, Power-Down Modes. [PDCR4 register in PFC setting ∗1] IERxD, IETxD pins enable [STBCR2 register setting ∗2] Module stop release [IECKSR register setting] Selection of clock supplied to IEB [IEAR1, IEAR2 register setting] Transmission mode Master address [IEIET, IEIER register setting] Interrupt enable Figure 20.8 Flowchart for Initial Setting |
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