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SH7261 Datasheet(PDF) 1007 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 1007 Page - Renesas Technology Corp |
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1007 / 1348 page ![]() Section 21 CD-ROM Decoder (ROM-DEC) Rev. 2.00 Sep. 07, 2007 Page 975 of 1312 REJ09B0320-0200 21.3.31 Post-ECC Correction Header: Frames (1/75 Seconds) Data Register (HEAD22) HEAD22 indicates the frames value (1 frame = 1/75 seconds) in the header after ECC correction. 76543210 Bit: Initial value: R/W: 00000000 RRRRRRRR HEAD22[7:0] Bit Bit Name Initial Value R/W Description 7 to 0 HEAD22[7:0] All 0 R Frames value in the header after ECC correction When MSF_LBA_SEL = 1, this register indicates the third byte of the total number of sectors calculated from M, S, and F. 21.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23) HEAD23 indicates the mode value in the header after ECC correction. 76543210 Bit: Initial value: R/W: 00000000 RRRRRRRR HEAD23[7:0] Bit Bit Name Initial Value R/W Description 7 to 0 HEAD23[7:0] All 0 R Mode value in the header after ECC correction |
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