SH7261 datasheet(122/1348 Pages) RENESAS

122 / 1348 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 07, 2007 Page 90 of 1312

REJ09B0320-0200

4.4.2

CKIO Control Register (CKIOCR)

CKIOCR is an 8-bit readable/writable register used to control output of the CKIO pin. When this

LSI is started in clock operating mode 3, writing 1 to this register is invalid.

When this LSI is started in clock operating mode 3, CKIOCR is initialized to H'00 by a power-on

reset caused by the

RES pin or in deep standby mode. When this LSI is started in clock operating

mode 0 or 2, CKIOCR is initialized to H'01 by a power-on reset caused by the

RES pin or in deep

standby mode. This register is not initialized by an internal reset triggered by an overflow of the

WDT, a manual reset, in sleep mode, or in software standby mode.

7654321

0/1*

RR/W

Bit:

Initial value:

R/W:

———

—

——

—

CKIO

Bit

Bit Name

Initial

Value

R/W

Description

7 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

CKIOOE

0/1*

R/W

CKIO Output Enable

Enables output of the CKIO pin.

0: Output from CKIO is not enabled.

1: Output from CKIO is enabled.

Note:

The initial value depends on the clock operating mode of the LSI.

SH7261 Datasheet(PDF) 122 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 122 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL