SH7261 datasheet(128/1348 Pages) RENESAS

128 / 1348 page

Section 5 Exception Handling

Rev. 2.00 Sep. 07, 2007 Page 96 of 1312

REJ09B0320-0200

Type

Exception Handling

Priority

A/D converter (ADC)

CD-ROM decoder (ROM-DEC)

Multifunction timer pulse unit 2 (MTU2)

Realtime clock (RTC)

Watchdog timer (WDT)

I²C bus interface 3 (IIC3)

Direct memory access controller (DMAC)

Serial communication interface with FIFO

(SCIF)

Controller area network (RCAN-ET)

IEBus

TM controller (IEB)

Serial sound interface (SSI)

Interrupts

On-chip peripheral modules

8-bit timer (TMR)

Trap instruction (TRAPA instruction)

General illegal instructions (undefined code)

Instructions

Slot illegal instructions (undefined code placed directly after a delayed

branch instruction*

1, instructions that rewrite the PC*2, 32-bit

instructions*

3, RESBANK instruction, DIVS instruction, and DIVU

instruction)

High

Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF.

2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.

3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,

BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,

MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.

SH7261 Datasheet(PDF) 128 Page - Renesas Technology Corp