SH7615 datasheet(55/925 Pages) RENESAS

55 / 925 page

Rev. 2.00, 03/05, page 17 of 884

Type

Symbol

I/O

Name

Function

System

control

RES

Input

Reset

When

RES = 0 and NMI = 1, the chip

enters the power-on reset state. When

RES = 0 and NMI = 0, the chip enters the

manual reset state

WDTOVF

Output

Watchdog

timer overflow

Counter overflow signal output in

watchdog timer mode

BGR

Output

Bus grant

Indicates that the bus has been released

to an external device. The device that

output the

BRLS signal recognizes that

the bus has been acquired when it

receives the

BGR signal

BRLS

Input

Bus release

Driven low when an external device

requests release of the bus

Operating

mode

MD0 to MD4 Input

Mode setting

The operating mode is specified by the

levels at these pins

Interrupts

NMI

Input

Nonmaskable

interrupt

Inputs the nonmaskable interrupt request

signal

IRL3 to IRL0 Input

External

interrupt

request input

0 to 3

These pins input maskable interrupt

request signals

IVECF

Output

Interrupt

vector fetch

cycle

Indicates an external vector read cycle

Bus control

Output

Bus cycle

start

Signal indicating the start of a bus cycle

Asserted every data cycle in burst

transfer

CS4 to CS0 Output

Chip select

0 to 4

Chip select signals indicating the area

being accessed

WAIT

Input

Wait

Wait state request signal

Output

Read

Strobe signal indicating a read cycle

RAS

Output

Row address

strobe

DRAM/synchronous DRAM RAS signal

SH7615 Datasheet(PDF) 55 Page - Renesas Technology Corp

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