SH7615 datasheet(32/925 Pages) RENESAS

32 / 925 page

Rev. 2.00, 03/05, page xxxii of xxxviii

10.1.1 Features................................................................................................................ 417

10.1.2 Configuration....................................................................................................... 418

10.1.3 Descriptor Management System .......................................................................... 419

10.1.4 Register Configuration......................................................................................... 419

10.2

Register Descriptions........................................................................................................ 421

10.2.1 E-DMAC Mode Register (EDMR)...................................................................... 421

10.2.2 E-DMAC Transmit Request Register (EDTRR) ................................................. 422

10.2.3 E-DMAC Receive Request Register (EDRRR)................................................... 423

10.2.4 Transmit Descriptor List Address Register (TDLAR)......................................... 424

10.2.5 Receive Descriptor List Address Register (RDLAR) .......................................... 425

10.2.6 EtherC/E-DMAC Status Register (EESR)........................................................... 426

10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)...................... 432

10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................ 437

10.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................... 438

10.2.10 Transmit FIFO Threshold Register (TFTR) ........................................................ 439

10.2.11 FIFO Depth Register (FDR) ................................................................................ 440

10.2.12 Receiver Control Register (RCR) ........................................................................ 443

10.2.13 E-DMAC Operation Control Register (EDOCR) ................................................ 444

10.2.14 Receiving-Buffer Write Address Register (RBWAR) ......................................... 445

10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) .................................... 446

10.2.16 Transmission-Buffer Read Address Register (TBRAR)...................................... 447

10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................... 448

10.3

Operation .......................................................................................................................... 449

10.3.1 Descriptor List and Data Buffers ......................................................................... 449

10.3.2 Transmission........................................................................................................ 455

10.3.3 Reception ............................................................................................................. 457

10.3.4 Multi-Buffer Frame Transmit/Receive Processing .............................................. 459

10.4

Usage Notes ...................................................................................................................... 461

10.4.1 E-DMAC Transmit Request Register (EDTRR) and E-DMAC Receive

Request Register (EDRRR) Usage Notes ............................................................ 461

Section 11 Direct Memory Access Controller (DMAC).......................................... 463

11.1

Overview........................................................................................................................... 463

11.1.1 Features................................................................................................................ 463

11.1.2 Block Diagram..................................................................................................... 465

11.1.3 Input/Output Pins................................................................................................. 466

11.1.4 Register Configuration......................................................................................... 467

11.2

Register Descriptions........................................................................................................ 468

11.2.1 DMA Source Address Registers 0 and 1 (SAR0, SAR1) .................................... 468

11.2.2 DMA Destination Address Registers 0 and 1 (DAR0, DAR1)............................ 468

11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1) ..................................... 469

11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1)............................. 470

11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1) ................. 474

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