SH7615 datasheet(30/925 Pages) RENESAS

30 / 925 page

Rev. 2.00, 03/05, page xxx of xxxviii

7.6.4

Wait State Control ............................................................................................... 330

7.6.5

Burst Access ........................................................................................................ 332

7.6.6

EDO Mode........................................................................................................... 335

7.6.7

DRAM Single Transfer........................................................................................ 339

7.6.8

Refreshing............................................................................................................ 340

7.6.9

Power-On Sequence............................................................................................. 342

7.7

Burst ROM Interface ........................................................................................................ 342

7.8

Idles between Cycles ........................................................................................................ 346

7.9

Bus Arbitration ................................................................................................................. 348

7.9.1

Master Mode........................................................................................................ 352

7.10

Additional Items ............................................................................................................... 353

7.10.1 Resets................................................................................................................... 353

7.10.2 Access as Viewed from CPU, DMAC or E-DMAC ............................................ 353

7.10.3 STATS1 and STATS0 Pins ................................................................................. 355

7.10.4

BUSHiZ Specification......................................................................................... 355

7.11

Usage Notes ...................................................................................................................... 356

7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC .... 356

7.11.2 When Using I

φ:Eφ Clock Ratio of 1:1, 8-Bit Bus Width,

and External Wait Input....................................................................................... 358

7.11.3 Preventing Wrong Data Output to Synchronous DRAM..................................... 358

Section 8 Cache.................................................................................................................... 359

8.1

Introduction ...................................................................................................................... 359

8.1.1

8.2

Register Description ......................................................................................................... 360

8.2.1

Cache Control Register (CCR) ............................................................................ 360

8.3

Address Space and the Cache ........................................................................................... 362

8.4

Cache Operation ............................................................................................................... 363

8.4.1

Cache Reads ........................................................................................................ 363

8.4.2

Write Access........................................................................................................ 365

8.4.3

Cache-Through Access ........................................................................................ 368

8.4.4

The TAS Instruction ............................................................................................ 368

8.4.5

Pseudo-LRU and Cache Replacement ................................................................. 368

8.4.6

Cache Initialization.............................................................................................. 370

8.4.7

Associative Purges............................................................................................... 370

8.4.8

Cache Flushing .................................................................................................... 371

8.4.9

Data Array Access ............................................................................................... 371

8.4.10 Address Array Access.......................................................................................... 372

8.5

Cache Use ......................................................................................................................... 373

8.5.1

Initialization......................................................................................................... 373

8.5.2

Purge of Specific Lines........................................................................................ 374

8.5.3

Cache Data Coherency......................................................................................... 374

8.5.4

Two-Way Cache Mode........................................................................................ 375

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