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H83008 Datasheet(PDF) 49 Page - Renesas Technology Corp |
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H83008 Datasheet(HTML) 49 Page - Renesas Technology Corp |
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49 / 686 page ![]() 1. Overview Rev.4.00 Aug. 20, 2007 Page 5 of 638 REJ09B0395-0400 1.2 Block Diagram Figure 1.1 shows an internal block diagram. Port 3 Port 4 A A A A 19 18 17 16 A A A A A A A A P9 /SCK / IRQ P9 /SCK / IRQ P9 /RxD P9 /RxD P9 /TxD P9 /TxD 5 4 3 2 1 0 1 0 1 0 1 0 5 4 Port 7 Port A CS0/P84 ADTRG/CS1/IRQ3/P83 CS2/IRQ2/P82 CS3/IRQ1/P81 IRQ0/P80 MD MD MD EXTAL XTAL STBY RES RESO NMI 2 1 0 H8/300H CPU Interrupt controller Serial communication interface (SCI) 2 channels × Watchdog timer (WDT) Address bus Data bus (upper) Data bus (lower) 15 14 13 12 11 10 9 8 A A A A A A A A 7 6 5 4 3 2 1 0 φ/P67 LWR HWR RD AS BACK/P62 BREQ/P61 WAIT/P60 RAM 16-bit timer unit 8-bit timer unit A/D converter D/A converter Programmable timing pattern controller (TPC) Port B Note: * The 5 V operation models have a V CL pin, and require the connection of an external capacitor. Figure 1.1 Block Diagram |
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