H83008 datasheet(13/686 Pages) RENESAS

13 / 686 page

Rev.4.00 Aug. 20, 2007, Page xiii of xliv

REJ09B0395-0400

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Page

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9.7.6 Contention

between TCOR Write

and Input Capture

Figure 9.23 Contention

between TCOR Write

and Input Capture

277

Figure amended

Address bus

TCOR address

Internal write signal

Input capture signal

8TCNT

TCOR write cycle

TCOR

9.7.7 Contention

between 8TCNT Byte

Write and Increment in

16-Bit Count Mode

(Cascaded Connection)

278

Description amended

If an increment pulse occurs in the T

2 or T3 state of an 8TCNT

byte write cycle in 16-bit count mode, the counter write takes

priority and the byte data for which the write was performed is

not incremented. The byte data for which a write was not

performed is incremented. Figure 9.24 shows the timing when

an increment pulse occurs in the T

2 state of a byte write to

8TCNT (upper byte). If an increment pulse occurs in the T

state, on the other hand, the increment takes priority.

Figure 9.24 Contention

between 8TCNT Byte

Write and Increment in

16-Bit Count Mode

Figure amended

Address bus

8TCNTH address

Internal write signal

8TCNT input clock

8TCNT (upper byte)

8TCNT write data

8TCNT (upper byte) byte write cycle

8TCNT (lower byte)

X + 1

N + 1

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