H83008 datasheet(86/686 Pages) RENESAS

86 / 686 page

2. CPU

Rev.4.00 Aug. 20, 2007 Page 42 of 638

REJ09B0395-0400

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits

of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is

added to the address register contents (32 bits) and the sum is stored in the address register.

The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or

longword access, the register value should be even.

• Register indirect with pre-decrement—@–ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the lower 24 bits of the result become the address of a memory

operand. The result is also stored in the address register. The value subtracted is 1 for byte

access, 2 for word access, or 4 for longword access. For word or longword access, the resulting

Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute

address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long

(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all

assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A

24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible

address ranges.

Table 2.12

Absolute Address Access Ranges

Absolute

Address

1-Mbyte Modes

16-Mbyte Modes

8 bits (@aa:8)

H'FFF00 to H'FFFFF

(1048320 to 1048575)

H'FFFF00 to H'FFFFFF

(16776960 to 16777215)

16 bits (@aa:16)

H'00000 to H'07FFF,

H'F8000 to H'FFFFF

(0 to 32767, 1015808 to 1048575)

H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

(0 to 32767, 16744448 to 16777215)

24 bits (@aa:24)

H'00000 to H'FFFFF

(0 to 1048575)

H'000000 to H'FFFFFF

(0 to 16777215)

Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit

(#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data

implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate

data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data

specifying a vector address.

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