H83008 datasheet(30/686 Pages) RENESAS

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Rev.4.00 Aug. 20, 2007 Page xxx of xliv

REJ09B0395-0400

Figure 5.3

Timing of Setting of IRQnF ...............................................................................

Figure 5.4

Process Up to Interrupt Acceptance when UE = 1 .............................................

Figure 5.5

Interrupt Masking State Transitions (Example) .................................................

Figure 5.6

Process Up to Interrupt Acceptance when UE = 0 .............................................

Figure 5.7

Interrupt Exception Handling Sequence.............................................................

Figure 5.8

Contention between Interrupt and Interrupt-Disabling Instruction ....................

Section 6 Bus Controller

Figure 6.1

Block Diagram of Bus Controller....................................................................... 102

Figure 6.2

Access Area Map for Each Operating Mode...................................................... 116

Figure 6.3

Memory Map in 16-Mbyte Mode....................................................................... 117

Figure 6.4

CSn Signal Output Timing (n = 0 to 7) .............................................................. 120

Figure 6.5

Sample Address Output in Each Address Update Mode

(Basic Bus Interface, 3-State Space) .................................................................. 120

Figure 6.6

Example of Consecutive External Space Accesses in Address Update

Mode 2 ............................................................................................................... 121

Figure 6.7

Access Sizes and Data Alignment Control (8-Bit Access Area) ........................ 122

Figure 6.8

Access Sizes and Data Alignment Control (16-Bit Access Area) ...................... 123

Figure 6.9

Bus Control Signal Timing for 8-Bit, Three-State-Access Area ........................ 125

Figure 6.10

Bus Control Signal Timing for 8-Bit, Two-State-Access Area .......................... 126

Figure 6.11

Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)

(Byte Access to Even Address) .......................................................................... 127

Figure 6.12

Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)

(Byte Access to Odd Address) ........................................................................... 128

Figure 6.13

Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)

(Word Access).................................................................................................... 129

Figure 6.14

Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)

(Byte Access to Even Address) .......................................................................... 130

Figure 6.15

Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)

(Byte Access to Odd Address) ........................................................................... 131

Figure 6.16

Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)

(Word Access).................................................................................................... 132

Figure 6.17

Example of Wait State Insertion Timing............................................................ 133

Figure 6.18

Example of Idle Cycle Operation (ICIS1 = 1).................................................... 134

Figure 6.19

Example of Idle Cycle Operation (ICIS0 = 1).................................................... 135

Figure 6.20

Example of Idle Cycle Operation ....................................................................... 136

Figure 6.21

Example of External Bus Master Operation....................................................... 138

Figure 6.22

ASTCR Write Timing ........................................................................................ 139

Figure 6.23

DDR Write Timing............................................................................................. 139

Figure 6.24

BRCR Write Timing .......................................................................................... 140

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