HD64F2602 datasheet(85/492 Pages) RENESAS

85 / 492 page

Section 4 Exception Handling

Rev. 1.00 Jan. 21, 2008 Page 53 of 456

REJ09B0425-0100

4.3

Reset

A reset has the highest exception priority.

When the

RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this

LSI is reset, hold the

RES pin low for at least 20 ms at power-up. To reset the chip during

operation, hold the

RES pin low for at least 20 states. A reset initializes the internal state of the

CPU and the registers of on-chip supporting modules.

The chip can also be reset by overflow of the watchdog timer. For details see section 12,

Watchdog Timer.

The interrupt control mode is 0 immediately after reset.

4.3.1

Reset Exception Handling

When the

RES pin goes high after being held low for the necessary time, this LSI starts reset

exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figures 4.1 and 4.2 show examples of the reset sequence.

HD64F2602 Datasheet(PDF) 85 Page - Renesas Technology Corp