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HD64F2602 Datasheet(PDF) 23 Page - Renesas Technology Corp |
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HD64F2602 Datasheet(HTML) 23 Page - Renesas Technology Corp |
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23 / 492 page  Rev. 1.00 Jan. 21, 2008 Page xxiii of xxxii Figure 10.19 Example of Cascaded Operation (2)...................................................................... 206 Figure 10.20 Example of PWM Mode Setting Procedure .......................................................... 209 Figure 10.21 Example of PWM Mode Operation (1) ................................................................. 210 Figure 10.22 Example of PWM Mode Operation (2) ................................................................. 210 Figure 10.23 Example of PWM Mode Operation (3) ................................................................. 211 Figure 10.24 Example of Phase Counting Mode Setting Procedure........................................... 213 Figure 10.25 Example of Phase Counting Mode 1 Operation .................................................... 213 Figure 10.26 Example of Phase Counting Mode 2 Operation .................................................... 214 Figure 10.27 Example of Phase Counting Mode 3 Operation .................................................... 215 Figure 10.28 Example of Phase Counting Mode 4 Operation .................................................... 216 Figure 10.29 Phase Counting Mode Application Example......................................................... 218 Figure 10.30 Count Timing in Internal Clock Operation............................................................ 222 Figure 10.31 Count Timing in External Clock Operation........................................................... 222 Figure 10.32 Output Compare Output Timing ........................................................................... 223 Figure 10.33 Input Capture Input Signal Timing........................................................................ 223 Figure 10.34 Counter Clear Timing (Compare Match) .............................................................. 224 Figure 10.35 Counter Clear Timing (Input Capture) .................................................................. 224 Figure 10.36 Buffer Operation Timing (Compare Match).......................................................... 225 Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................. 225 Figure 10.38 TGI Interrupt Timing (Compare Match) ............................................................... 226 Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................... 227 Figure 10.40 TCIV Interrupt Setting Timing.............................................................................. 228 Figure 10.41 TCIU Interrupt Setting Timing.............................................................................. 229 Figure 10.42 Timing for Status Flag Clearing by CPU .............................................................. 229 Figure 10.43 Timing for Status Flag Clearing by DTC Activation ............................................ 230 Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 231 Figure 10.45 Contention between TCNT Write and Clear Operations....................................... 232 Figure 10.46 Contention between TCNT Write and Increment Operations ............................... 233 Figure 10.47 Contention between TGR Write and Compare Match........................................... 234 Figure 10.48 Contention between Buffer Register Write and Compare Match.......................... 235 Figure 10.49 Contention between TGR Read and Input Capture ............................................... 236 Figure 10.50 Contention between TGR Write and Input Capture .............................................. 237 Figure 10.51 Contention between Buffer Register Write and Input Capture.............................. 238 Figure 10.52 Contention between Overflow and Counter Clearing............................................ 239 Figure 10.53 Contention between TCNT Write and Overflow................................................... 240 Section 11 Programmable Pulse Generator (PPG) Figure 11.1 Block Diagram of PPG............................................................................................ 242 Figure 11.2 PPG Output Operation............................................................................................. 251 Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 252 Figure 11.4 Setup Procedure for Normal Pulse Output (Example)............................................. 253 |
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