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HD64F2602 Datasheet(PDF) 21 Page - Renesas Technology Corp |
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HD64F2602 Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 492 page  Rev. 1.00 Jan. 21, 2008 Page xxi of xxxii Figures Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 2 Figure 1.2 Pin Arrangement............................................................................................................ 3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 13 Figure 2.2 Stack Structure in Normal Mode................................................................................. 13 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 14 Figure 2.4 Stack Structure in Advanced Mode............................................................................. 15 Figure 2.5 Memory Map............................................................................................................... 16 Figure 2.6 CPU Registers ............................................................................................................. 17 Figure 2.7 Usage of General Registers .........................................................................................18 Figure 2.8 Stack............................................................................................................................ 19 Figure 2.9 General Register Data Formats (1).............................................................................. 22 Figure 2.9 General Register Data Formats (2).............................................................................. 23 Figure 2.10 Memory Data Formats...............................................................................................24 Figure 2.11 Instruction Formats (Examples) ................................................................................ 36 Figure 2.12 Branch Address Specification in Memory Indirect Mode ......................................... 40 Figure 2.13 State Transitions ........................................................................................................ 44 Section 3 MCU Operating Modes Figure 3.1 Address Map ............................................................................................................... 49 Section 4 Exception Handling Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)............................... 54 Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled: Cannot be Used in this LSI) ....................................................................................... 55 Figure 4.3 Stack Status after Exception Handling ........................................................................ 59 Figure 4.4 Operation when SP Value is Odd................................................................................ 60 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 62 Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5 ................................................................ 69 Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 ............................................................................................ 74 Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2..................... 76 Figure 5.5 Interrupt Exception Handling ......................................................................................78 Figure 5.6 Contention between Interrupt Generation and Disabling ............................................ 81 |
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