HD6433045 datasheet(49/905 Pages) RENESAS

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Section 2 CPU

Rev. 7.00 Sep 21, 2005 page 25 of 878

REJ09B0259-0700

Section 2 CPU

2.1

Overview

The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general

registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

2.1.1

Features

The H8/300H CPU has the following features.

Upward compatibility with H8/300 CPU

Can execute H8/300 Series object programs

General-register architecture

Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)

Sixty-two basic instructions

 8/16/32-bit data transfer and arithmetic and logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, or @aa:24]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8, PC) or @(d:16, PC)]

 Memory indirect [@@aa:8]

16-Mbyte linear address space

High-speed operation

 All frequently-used instructions execute in two to four states

 Maximum clock frequency:

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