HD6433045 datasheet(74/905 Pages) RENESAS

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Section 2 CPU

Rev. 7.00 Sep 21, 2005 page 50 of 878

REJ09B0259-0700

2.7

Addressing Modes and Effective Address Calculation

2.7.1

Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses

a subset of these addressing modes. Arithmetic and logic instructions can use the register direct

and immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit manipulation instructions use register direct, register

indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,

BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit

number in the operand.

Table 2.11 Addressing Modes

No.

Addressing Mode

Symbol

@ERn

@(d:16, ERn)/@(d:24, ERn)

@ERn+

@–ERn

Absolute address

@aa:8/@aa:16/@aa:24

Immediate

#xx:8/#xx:16/#xx:32

Program-counter relative

@(d:8, PC)/@(d:16, PC)

Memory indirect

@@aa:8

1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit

R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit

registers.

2 Register Indirect—@ERn: The register field of the instruction code specifies an address

3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit

displacement contained in the instruction code is added to the contents of an address register

(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the

address of a memory operand. A 16-bit displacement is sign-extended when added.

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