HD6433045 datasheet(28/905 Pages) RENESAS

28 / 905 page

Section 1 Overview

Rev. 7.00 Sep 21, 2005 page 4 of 878

REJ09B0259-0700

Feature

Description

DMA controller

(DMAC)

• Short address mode

 Maximum four channels available

 Selection of I/O mode, idle mode, or repeat mode

 Can be activated by compare match/input capture A interrupts from ITU

channels 0 to 3, transmit-data-empty and receive-data-full interrupts from

SCI channel 0, or external requests

• Full address mode

 Maximum two channels available

 Selection of normal mode or block transfer mode

 Can be activated by compare match/input capture A interrupts from ITU

channels 0 to 3, external requests, or auto-request

16-bit integrated

timer unit (ITU)

• Five 16-bit timer channels, capable of processing up to 12 pulse outputs or

10 pulse inputs

• 16-bit timer counter (channels 0 to 4)

• Two multiplexed output compare/input capture pins (channels 0 to 4)

• Operation can be synchronized (channels 0 to 4)

• PWM mode available (channels 0 to 4)

• Phase counting mode available (channel 2)

• Buffering available (channels 3 and 4)

• Reset-synchronized PWM mode available (channels 3 and 4)

• Complementary PWM mode available (channels 3 and 4)

• DMAC can be activated by compare match/input capture A interrupts

(channels 0 to 3)

Programmable

timing pattern

controller (TPC)

• Maximum 16-bit pulse output, using ITU as time base

• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)

• Non-overlap mode available

• Output data can be transferred by DMAC

Watchdog timer

(WDT),

1 channel

• Reset signal can be generated by overflow

• Reset signal can be output externally

• Usable as an interval timer

HD6433045 Datasheet(PDF) 28 Page - Renesas Technology Corp

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