R8C18 datasheet(60/257 Pages) RENESAS

60 / 257 page

R8C/18 Group, R8C/19 Group

7. Voltage Detection Circuit

Rev.1.30

Apr 14, 2006

Page 45 of 233

REJ09B0222-0130

Figure 7.6

VW2C Register

Voltage Monitor 2 Circuit Control Register

(1)

Symbol

Address

After Reset(8)

VW2C

0037h

00h

Bit Symbol

Bit Name

Function

NOTES:

10.

When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2 or

below ). (Do not set to 0.)

Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to this register.

When rew riting the VW2C register, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the VW2C

When the voltage monitor 2 interrupt is used to exit stop mode and to return again, w rite 0 to the VW2C1bit before

w riting 1.

This bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).

Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is

w ritten to it).

This bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enabled reset).

The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit

enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).

The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode).

Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, or voltage monitor 2

VW2C7

Voltage monitor 2 interrupt/reset

generation condition select bit(7, 9)

0 : When VCC reaches Vdet2 or above.

1 : When VCC reaches Vdet2 or below .

VW2C6

Voltage monitor 2 circuit mode

select bit(5)

0 : Voltage monitor 2 interrupt mode

1 : Voltage monitor 2 reset mode

VW2F1

Sampling clock select bits

b5 b4

0 0 : fRING-S divide by 1

0 1 : fRING-S divide by 2

1 0 : fRING-S divide by 4

1 1 : fRING-S divide by 8

VW2F0

Voltage monitor 2 interrupt/reset

enable bit(6, 10)

VW2C3

WDT detection flag(4, 8)

0 : Not detected

1 : Detected

0 : Digital filter enabled mode

(digital filter circuit enabled)

1 : Digital filter disabled mode

(digital filter circuit disabled)

VW2C2

Voltage change detection flag(3, 4, 8)

VW2C1

Voltage monitor 2 digital filter

disable mode select bit(2)

0 : Disable

1 : Enable

VW2C0

b7 b6 b5 b4

Set the VW2C0 bit to 0 (disabled) w hen the VCA13 bit in the VCA1 register is set to 1 (VCC

≥ Vdet2 or voltage

detection 2 circuit disabled), the VW2C1 bit is set to 1 (digital filter disabled mode), and the VW2C7 bit is set to 0

(w hen VCC reaches Vdet2 or above).

Set the VW2C0 bit to 0 (disabled) w hen the VCA13 bit is set to 0 (VCC < Vdet2), the VW2C1 bit is set to 1 (digital

filter disabled mode), and the VW2C7 bit is set to 1 (w hen VCC reaches Vdet2 or below ).

0 : Not detected

1 : Vdet2 crossing detected

b1 b0

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