R8C18 datasheet(93/257 Pages) RENESAS

93 / 257 page

R8C/18 Group, R8C/19 Group

12. Interrupts

Rev.1.30

Apr 14, 2006

Page 78 of 233

REJ09B0222-0130

Figure 12.4

INT0IC Register

INT0 Interrupt Control Register

(2)

Symbol

Address

After Reset

INT01C

005Dh

XX00X000b

Bit Symbol

Bit Name

Function

NOTES:

—

(b7-b6)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Only 0 can be w ritten to the IR bit. (Do not w rite 1.)

—

(b5)

Reserved bit

Set to 0.

POL

Polarity sw itch bit(4)

0 : Selects falling edge.

1 : Selects rising edge.(3)

Interrupt request bit

0 : Requests no interrupt.

1 : Requests interrupt.

RW(1)

ILVL0

Interrupt priority level select bits

b2 b1 b0

0 0 0 : Level 0 (interrupt disable)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

ILVL1

ILVL2

Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.

Refer to 12.5.6 Changing Interrupt Control Register Contents.

If the INTOPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).

The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12.5.5 Changing Interrupt

Sources.

b7 b6 b5 b4 b3 b2 b1

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