M30245 datasheet(55/367 Pages) RENESAS

55 / 367 page

Rev.2.00 Oct 16, 2006

page 46 of 354

REJ09B0340-0200

M30245 Group

2. Clock-Synchronous Serial I/O

D0 D1 D2 D3

D4 D5 D6

D0 D1

D2 D3 D4 D5 D6 D7

TCLK

Stopped pulsing because

transfer enable bit = “0”

Tc = TCLK = 2(n + 1) / fi

fi: frequency of BRGi count source (f1, f8, f32)

n: value set to BRGi

Transfer clock

Transmit

enable bit (TE)

Transmit

buffer empty

flag (Tl)

CLKi

TxDi

Transmit register

empty flag

(TXEPT)

“H”

“L”

“0”

“1”

“0”

“1”

“0”

“1”

CTSi

Transmit

interrupt request

bit (IR)

“0”

“1”

Cleared to “0” when interrupt request is accepted, or cleared by software

D0 D1

D2 D3

D4 D5 D6

(1) Transmission enabled

(2) Confirming CTS

(3) Start transmission Tc

(4) Transmission is complete

(5) Transmit next data

Data is set to UARTi transmit buffer register

Stopped pulsing because CTSi = “H”

Shown in ( ) are bit symbols.

The above timing applies to the following settings:

• Internal clock is selected.

• CTS function is selected.

• CLK polarity select bit = “0”.

• Transmit interrupt cause select bit = “0”.

Transferred from UARTi transmit buffer register to UARTi transmit register

Example of wiring

CLKi

TXDi

CTSi

CLK

RXD

Port

Microcomputer

Receiver side IC

(Note)

Note : Since TXD2 pin is N-channel open drain,

this pin needs pull-up resistance.

Figure 2.3.5. Operation timing of transmission in clock-synchronous serial I/O mode

Example of operation

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