SH7049 datasheet(13/764 Pages) RENESAS

13 / 764 page

Rev. 2.00, 09/04, page xiii of xl

9.7.1

Prevention of Data Bus Conflicts......................................................................... 145

9.7.2

Simplification of Bus Cycle Start Detection........................................................ 145

9.8

Bus Arbitration.................................................................................................................. 146

9.9

Memory Connection Example .......................................................................................... 147

9.10

On-chip Peripheral I/O Register Access ........................................................................... 148

9.11

Cycles in which Bus is not Released................................................................................. 148

9.12

CPU Operation when Program is In External Memory .................................................... 148

Section 10 Multi-Function Timer Pulse Unit (MTU) ........................................149

10.1

Features............................................................................................................................. 149

10.2

Input/Output Pins .............................................................................................................. 153

10.3

Register Descriptions ........................................................................................................ 154

10.3.1 Timer Control Register (TCR)............................................................................. 156

10.3.2 Timer Mode Register (TMDR) ............................................................................ 160

10.3.3 Timer I/O Control Register (TIOR) ..................................................................... 162

10.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 180

10.3.5 Timer Status Register (TSR)................................................................................ 182

10.3.6 Timer Counter (TCNT)........................................................................................ 185

10.3.7 Timer General Register (TGR) ............................................................................ 185

10.3.8 Timer Start Register (TSTR) ............................................................................... 186

10.3.9 Timer Synchro Register (TSYR) ......................................................................... 187

10.3.10 Timer Output Master Enable Register (TOER) ................................................... 188

10.3.11 Timer Output Control Register (TOCR) .............................................................. 189

10.3.12 Timer Gate Control Register (TGCR) ................................................................. 191

10.3.13 Timer Subcounter (TCNTS) ................................................................................ 192

10.3.14 Timer Dead Time Data Register (TDDR)............................................................ 192

10.3.15 Timer Period Data Register (TCDR) ................................................................... 193

10.3.16 Timer Period Buffer Register (TCBR)................................................................. 193

10.3.17 Bus Master Interface ............................................................................................ 193

10.4

Operation .......................................................................................................................... 194

10.4.1 Basic Functions.................................................................................................... 194

10.4.2 Synchronous Operation........................................................................................ 200

10.4.3 Buffer Operation .................................................................................................. 202

10.4.4 Cascaded Operation ............................................................................................. 206

10.4.5 PWM Modes ........................................................................................................ 207

10.4.6 Phase Counting Mode .......................................................................................... 212

10.4.7 Reset-Synchronized PWM Mode......................................................................... 218

10.4.8 Complementary PWM Mode............................................................................... 222

10.5

Interrupts........................................................................................................................... 247

10.5.1 Interrupts and Priorities........................................................................................ 247

10.5.2 DTC Activation.................................................................................................... 249

10.5.3 A/D Converter Activation.................................................................................... 249

10.6

Operation Timing.............................................................................................................. 250

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