SH7049 datasheet(32/764 Pages) RENESAS

32 / 764 page

Rev. 2.00, 09/04, page xxxii of xl

Figure 19.2 Flash Memory State Transitions.............................................................................. 551

Figure 19.3 Boot Mode............................................................................................................... 552

Figure 19.4 User Program Mode ................................................................................................ 553

Figure 19.5 Flash Memory Block Configuration........................................................................ 554

Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode........................ 562

Figure 19.7 Flowchart for Flash Memory Emulation in RAM ................................................... 563

Figure 19.8 Example of RAM Overlap Operation (RAM[2:0]

= b'000) .................................... 564

Figure 19.9 Program/Program-Verify Flowchart ....................................................................... 566

Figure 19.10 Erase/Erase-Verify Flowchart ............................................................................... 568

Figure 19.11 Power-On/Off Timing (Boot Mode) ..................................................................... 574

Figure 19.12 Power-On/Off Timing (User Program Mode) ....................................................... 575

Figure 19.13 Mode Transition Timing

(Example: Boot Mode

→ User Mode →User Program Mode) ............................. 576

Section 20 Mask ROM

Figure 20.1 Mask ROM Block Diagram .................................................................................... 577

Section 22 High-Performance User Debugging Interface (H-UDI)

Figure 22.1 H-UDI Block Diagram ............................................................................................ 582

Figure 22.2 Data Input/Output Timing Chart (1)........................................................................ 588

Figure 22.3 Data Input/Output Timing Chart (2)........................................................................ 589

Figure 22.4 Data Input/Output Timing Chart (3)........................................................................ 589

Figure 22.5 Serial Data Input/Output ......................................................................................... 591

Section 23 Advanced User Debugger (AUD)

Figure 23.1 AUD Block Diagram............................................................................................... 594

Figure 23.2 Example of Data Output (32-Bit Output)................................................................ 598

Figure 23.3 Example of Output in Case of Successive Branches ............................................... 598

Figure 23.4 AUDATA Input Format .......................................................................................... 599

Figure 23.5 Example of Read Operation (Byte Read)................................................................ 600

Figure 23.6 Example of Write Operation (Longword Write) ..................................................... 600

Figure 23.7 Example of Error Occurrence (Longword Read) .................................................... 600

Section 24 Power-Down Modes

Figure 24.1 Mode Transition Diagram ....................................................................................... 605

Figure 24.2 NMI Timing in Software Standby Mode................................................................. 614

Figure 24.3 Transition Timing to Hardware Standby Mode....................................................... 615

Figure 24.4 Example of External Circuit Connected to

HSTBY Pin ......................................... 616

Section 25 Electrical Characteristics

Figure 25.1 Output Load Circuit ................................................................................................ 623

Figure 25.2 System Clock Timing.............................................................................................. 625

Figure 25.3 EXTAL Clock Input Timing ................................................................................... 625

Figure 25.4 Oscillation Settling Time.........................................................................................625

Figure 25.5 Reset Input Timing.................................................................................................. 627

Figure 25.6 Reset Input Timing.................................................................................................. 627

SH7049 Datasheet(PDF) 32 Page - Renesas Technology Corp

SH7049 Datasheet(HTML) 32 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL