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SH7052 Datasheet(PDF) 374 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 374 Page - Renesas Technology Corp |
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374 / 919 page ![]() 348 Pø TST6A TCNT6A Clock TCNT6A CYLR6A BFR6A DTR6A TO6A TSR6 Write to BFR6A No PWM output for 1 cycle after activation Cycle Cycle Cycle Data = 0000 Data = 0004 Data = 0001 Cycle Duty = 100% Cycle Duty = 0% Cleared by software Cleared by software Cleared by software 0001 0004 0000 0002 0002 0004 0003 0002 0001 0004 0003 0002 0001 0004 0003 0002 0001 0004 0003 0002 0001 0001 0002 0003 0004 0001 0004 0000 Figure 10.21 PWM Timer Operation Channel 6 can be used in complementary PWM mode by making a setting in the PWM mode control register (PMDR). On-duty or off-duty can also be selected with a setting in PMDR. When TCNT6 is started by a setting in TSTR, it starts counting up. When TCNT6 reaches the CYLR6 value, it starts counting down, and on reaching H'000, starts counting up again. The counter status is shown by TSR6. When TCNT6 underflows, an interrupt request can be sent to the CPU by setting the corresponding bit in TIER. When TCNT6 matches the duty register (DTR6) value, the output is inverted. The output prior to the match depends on the PMDR setting. When a value including dead time is set in DTR6, a maximum of 4-phase PWM output is possible. Data transfer from BFR6 to DTR6 is performed when TCNT6 underflows. An example of channel 6 complementary PWM mode operation is shown in figure 10.22. In the example in figure 10.22, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0003, H'0004 (100%), and H'0000 (0%) in BFR6A. |
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