SH7052 datasheet(379/919 Pages) RENESAS

379 / 919 page

353

Pø

TI10

TCNT10H

φ × 10

(clock)

NCR10

AGCK

External edge mask period

Note: When rising and falling edges are set

Noise

cancellation

period

AGCK

operation

TCNT clock

Figure 10.27 Edge Input Operation (With Noise Cancellation)

Pø

TSTR

TST10

TCNT10A

Clock

AGCK

ICR10A

OCR10A

Capture

transfer

signal

TCNT reset

signal

TSR10

CMF10A

TSR10

IMF10A

1234

5678

Cleared by software

55555556

Cleared by software

12345678

00000000

55555556

55555557

55555555

00000000

12345677

00000003

00000001

00000002

Figure 10.28 TCNT10A Capture Operation and Compare-Match Operation

Internally synchronized AGCK is counted by event count 10B (TCNT10B), and when TCNT10B

reaches the value set beforehand in compare-match register 10B (OCR10B), a compare-match

occurs, and the compare-match trigger signal is transmitted to channel 0. By setting the

corresponding bit in TIER, an interrupt request can be sent to the CPU.

SH7052 Datasheet(PDF) 379 Page - Renesas Technology Corp

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