SH7052 datasheet(403/919 Pages) RENESAS

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Sample Setup Procedure for Offset One-Shot Pulse Output/Cutoff Operation: An example of

the setup procedure for offset one-shot pulse output is shown in figure 10.57.

1. Set the first-stage counter clock ø' in prescaler register 1 (PSCR1), and select the second-stage

counter clock ø" with the CKSEL bit in the timer control register (TCR1, TCR2, TCR8).

2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output

port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO

3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2).

If necessary, a timer interrupt request can be sent to the CPU when the down-counter

underflows by making the appropriate setting in the interrupt enable register (TIER8).

4. Set the offset width in the channel 1 or 2 general register (GR1A to GR1H, GR2A to GR2H)

connected to the down-counter (DCNT) corresponding to the port set in 2, and in the output

compare register (OCR1, OCR2A to OCR2H). Set the timer I/O control register (TIOR1A to

TIOR1D, TIOR2A to TIOR2D) to the compare-match enabled state.

5. Set the start/terminate trigger by means of the trigger mode register (TRGMDR), timer

connection register (TCNR), and one-shot pulse terminate register (OTR), so that it

corresponds to the port set in step 2 above.

6. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 or 2 free-

running counter (TCNT1, TCNT2). When the TCNT value and GR value or OCR value

match, the corresponding DCNT starts counting down or is forcibly cleared, and one-shot

pulse output is performed.

SH7052 Datasheet(PDF) 403 Page - Renesas Technology Corp