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SH7052 Datasheet(PDF) 413 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 413 Page - Renesas Technology Corp |
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413 / 919 page  387 10.7 Usage Notes Note that the kinds of operation and contention described below occur during ATU operation. Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 7 free- running counters (TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D), if a compare-match occurs in the T2 state of a CPU write cycle when counter clearing by compare- match has been set, or when PWM mode is used, the write to TCNT has priority and TCNT clearing is not performed. The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform output to an external destination are performed in the same way as for a normal compare-match. The timing in this case is shown in figure 10.64. Pø T1 Address TCNT address CPU write value Internal write signal Compare-match signal Counter clear signal TCNT Interrupt status flag External output signal (1 output) T2 Figure 10.64 Contention between TCNT Write and Clear |
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