SH7052 datasheet(451/919 Pages) RENESAS

451 / 919 page

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12.4.4

System Reset by

WDTOVF Signal

If a

WDTOVF signal is input to the RES pin, the chip cannot initialize correctly.

Avoid logical input of the

WDTOVF output signal to the RES input pin. To reset the entire system

with the

WDTOVF signal, use the circuit shown in figure 12.9.

Reset input

Reset signal to

entire system

SH7052F, SH7053F, SH7054F

RES

WDTOVF

Figure 12.9 Example of System Reset Circuit Using

WDTOVF Signal

12.4.5

Internal Reset in Watchdog Timer Mode

If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a

TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset.

12.4.6

Manual Reset in Watchdog Timer

When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits

until the end of the bus cycle at the time of manual reset generation before making the transition to

manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a

manual reset occurs while the bus is released or during DMAC burst transfer, manual reset

exception processing will be deferred until the CPU acquires the bus. However, if the interval

from generation of the manual reset until the end of the bus cycle is equal to or longer than the

internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of

being deferred, and manual reset exception processing is not executed.

SH7052 Datasheet(PDF) 451 Page - Renesas Technology Corp