SH7052 datasheet(455/919 Pages) RENESAS

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13.1.3

Table 13.1 summarizes the CMT register configuration.

Table 13.1

Channel Name

Abbreviation

R/W

Initial

Value

Address

Access Size

(Bits)

Shared

Compare match timer

start register

CMSTR

R/W

H'0000

H'FFFFF710 8, 16, 32

Compare match timer

control/status register 0

CMCSR0

R/(W)*

H'0000

H'FFFFF712 8, 16, 32

Compare match timer

counter 0

CMCNT0

R/W

H'0000

H'FFFFF714 8, 16, 32

Compare match timer

constant register 0

CMCOR0

R/W

H'FFFF

H'FFFFF716 8, 16, 32

Compare match timer

control/status register 1

CMCSR1

R/(W)*

H'0000

H'FFFFF718 8, 16, 32

Compare match timer

counter 1

CMCNT1

R/W

H'0000

H'FFFFF71A 8, 16, 32

Compare match timer

constant register 1

CMCOR1

R/W

H'FFFF

H'FFFFF71C 8, 16, 32

Notes: 1. The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to

clear the flags.

2. With regard to access size, four or five cycles are required for byte access and word

access, and eight or nine cycles for longword access.

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