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SH7052 Datasheet(PDF) 456 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 456 Page - Renesas Technology Corp |
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456 / 919 page  430 13.2 Register Descriptions 13.2.1 Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 14 13 12 11 10 9 8 —— —— ——— — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — STR1 STR0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W • Bits 15 to 2—Reserved: These bits always read 0. The write value should always be 0. • Bit 1—Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1. Bit 1: STR1 Description 0 CMCNT1 count operation halted (Initial value) 1 CMCNT1 count operation • Bit 0—Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0. Bit 0: STR0 Description 0 CMCNT0 count operation halted (Initial value) 1 CMCNT0 count operation |
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