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SH7052 Datasheet(PDF) 482 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 482 Page - Renesas Technology Corp

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14.2.8
Bit Rate Register (BRR)
The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to BRR. BRR is initialized to H'FF by a power-on reset and in
hardware standby mode. It is not initialized by a manual reset, and in software standby mode.
Each channel has independent baud rate generator control, so different values can be set for each
channel.
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 14.3 lists examples of BRR settings in the asynchronous mode; table 14.4 lists examples of
BBR settings in the clock synchronous mode.
The BRR setting is calculated as follows:
Asynchronous mode:
N =
64
× 22n–1 × B
× 106 – 1
P
φ
Synchronous mode:
N =
8
× 22n–1 × B
× 106 – 1
P
φ
B:
Bit rate (bits/s)
N:
Baud rate generator BRR setting (0
≤ N ≤ 255)
P
φ: Peripheral module operating frequency (MHz) (1/2 of system clock)
n:
Baud rate generator input clock (n = 0 to 3)
(See the following table for the clock sources and value of n.)
SMR Settings
n
Clock Source
CKS1
CKS2
0P
φ
00
1P
φ/4
0
1
2P
φ/16
1
0
3P
φ/64
1
1



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