SH7052 datasheet(478/919 Pages) RENESAS

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14.2.7

Serial Status Register (SSR)

The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status

flags that indicate the SCI operating status.

The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF,

ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after

being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is

initialized to H'84 by a power-on reset, and in hardware standby mode and software standby mode.

It is not initialized by a manual reset.

Bit:

TDRE

RDRF

ORER

FER

PER

TEND

MPB

MPBT

Initial value:

R/W:

R/(W)*

R/W

Note: * The only value that can be written is a 0 to clear the flag.

• Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data

from TDR into TSR and new serial transmit data can be written in TDR.

Bit 7: TDRE

Description

TDR contains valid transmit data

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC writes data in TDR

TDR does not contain valid transmit data

(Initial value)

[Setting conditions]

• Power-on reset, hardware standby mode, or software standby mode

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR, enabling new data to be written in

TDR

SH7052 Datasheet(PDF) 478 Page - Renesas Technology Corp