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SH7052 Datasheet(PDF) 633 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 633 Page - Renesas Technology Corp |
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633 / 919 page  607 18.3 Register Descriptions 18.3.1 Port A IO Register (PAIOR) Bit: 15 14 13 12 11 10 9 8 PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR Initial value: 00 00 000 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR Initial value: 00 00 000 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W The port A IO register (PAIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port A. Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0 to PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to PA0) or ATU input/output pins, and disabled otherwise. For bits 3 to 0, when ATU input capture input is selected, the PAIOR bits should be cleared to 0. When port A pins function as PA15 to PA0 or ATU input/output pins, a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 18.3.2 Port A Control Registers H and L (PACRH, PACRL) Port A control registers H and L (PACRH, PACRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port A. PACRH selects the functions of the pins for the upper 8 bits of port A, and PACRL selects the functions of the pins for the lower 8 bits. PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. |
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