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SH7052 Datasheet(PDF) 644 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 644 Page - Renesas Technology Corp |
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644 / 919 page ![]() 618 18.3.5 Port B Invert Register (PBIR) Bit: 15 14 13 12 11 10 9 8 PB15IR PB14IR PB13IR — PB11IR PB10IR PB9IR PB8IR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PB7IR PB6IR PB5IR PB4IR PB3IR PB2IR PB1IR PB0IR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W The port B invert register (PBIR) is a 16-bit readable/writable register that sets the port B inversion function. Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins PB15/PULS5/SCK2 to PB13/SCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled when port B pins function as ATU outputs or serial clock pins, and disabled otherwise. When port B pins function as ATU outputs or serial clock pins, the value of a pin is inverted when the corresponding bit in PBIR is set to 1. PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PBnIR Description 0 Value is not inverted (Initial value) 1 Value is inverted n = 15 to 0 |
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