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SH7052 Datasheet(PDF) 648 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 648 Page - Renesas Technology Corp |
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648 / 919 page ![]() 622 18.3.8 Port D IO Register (PDIOR) Bit: 15 14 13 12 11 10 9 8 — — PD13 IOR PD12 IOR PD11 IOR PD10 IOR PD9 IOR PC8 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PD7 IOR PD6 IOR PD5 IOR PD4 IOR PD3 IOR PD2 IOR PD1 IOR PD0 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W The port D IO register (PDIOR) is a 16-bit readable/writable register that selects the input/output direction of the 14 pins in port D. Bits PD13IOR to PD0IOR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. PDIOR is enabled when port D pins function as general input/output pins (PD13 to PD0) or timer input/output pins, and disabled otherwise. When port D pins function as PD13 to PD0 or timer input/output pins, a pin becomes an output when the corresponding bit in PDIOR is set to 1, and an input when the bit is cleared to 0. PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. |
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