SH7052 datasheet(721/919 Pages) RENESAS

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20.4

The registers used to control the on-chip flash memory when enabled are shown in table 20.3.

Table 20.3

Abbreviation

R/W

Initial Value

Address

Access Size

Flash memory control

FLMCR1

R/W*

H'00*

H'FFFFE800

Flash memory control

FLMCR2

R/W*

H'00

H'FFFFE801

Erase block register 1

EBR1

R/W*

H'00*

H'FFFFE802

Erase block register 2

EBR2

R/W*

H'00*

H'FFFFE803

RAM emulation register

RAMER

R/W

H'0000

H'FFFFEC26

8, 16, 32

Notes: 1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and

writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1.

2. When a high level is input to the FWE pin, the initial value is H'80.

3. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in

FLMCR1 is not set, these registers are initialized to H'00.

4. Will be initialized to H'00 if a low level is input to pin FWE or if bit SWE2 of FLMCR2 is

not set even though a high level is input.

5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers, and RAMER is a 16-bit

6. Only byte accesses are valid for FLMCR1, FLMCR2, EBR1, and EBR2, the access

requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and

6 cycles for a longword access.

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