SH7052 datasheet(745/919 Pages) RENESAS

745 / 919 page

719

2. When a SLEEP instruction (including software standby) is executed during

programming/erasing

Error protection is released only by a power-on reset and in hardware standby mode.

Figure 20.16 shows the flash memory state transition diagram.

RD VF PR ER FLER = 0

Error

occurrence

RES = 0 or HSTBY = 0

RES = 0 or

HSTBY = 0

RD VF PR ER FLER = 0

Program mode

Erase mode

Reset or standby

(hardware protection)

RD VF PR ER FLER = 1

Error protection mode

(software standby)

Software

standby mode

FLMCR1, FLMCR2, EBR1,

EBR2 initialization state

FLMCR1, FLMCR2,

EBR1, EBR2

initialization state

Software standby

mode release

RD: Memory read possible

VF: Verify-read possible

PR: Programming possible

ER: Erasing possible

RD: Memory read not possible

VF: Verify-read not possible

PR: Programming not possible

ER: Erasing not possible

Legend

RES = 0 or

HSTBY = 0

Error occurrence

(software standby)

RD VF PR ER FLER = 1

Figure 20.16 Flash Memory State Transitions

SH7052 Datasheet(PDF) 745 Page - Renesas Technology Corp

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